What procedure do I need in order to build the core for an Arty-A7 100T ?

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bonnefoiopened 6mo ago

Hello,

I've installed litex and verilator on a Ubuntu 24.04 LTS distro : I've used the litex_setup.py provided inside the /deps directory inside a virtual environment.

Then, I've tried the 'verilate.sh' script and get an error related to litex :

❯ ./verilate.sh
Target: iron
Speed: normal
CPU: vexi
--------------------- BUILD CORE --------------------
Traceback (most recent call last):
  File "/home/pef/DEMO_BAOCHIP/baochip-1x/verilate/./bao_core.py", line 14, in <module>
    import litex.soc.doc as lxsocdoc
  File "/home/pef/DEMO_BAOCHIP/baochip-1x/deps/litex/litex/soc/doc/__init__.py", line 12, in <module>
    from litex.soc.integration import export
  File "/home/pef/DEMO_BAOCHIP/baochip-1x/deps/litex/litex/soc/integration/export.py", line 36, in <module>
    from litex.soc.doc.module import gather_submodules, ModuleNotDocumented, DocumentedModule, DocumentedInterrupts
  File "/home/pef/DEMO_BAOCHIP/baochip-1x/deps/litex/litex/soc/doc/module.py", line 10, in <module>
    from litex.soc.interconnect.csr_eventmanager import EventManager
  File "/home/pef/DEMO_BAOCHIP/baochip-1x/deps/litex/litex/soc/interconnect/csr_eventmanager.py", line 17, in <module>
    from litex.gen import *
  File "/home/pef/DEMO_BAOCHIP/baochip-1x/deps/litex/litex/gen/__init__.py", line 3, in <module>
    from litex.gen.fhdl.module import *
  File "/home/pef/DEMO_BAOCHIP/baochip-1x/deps/litex/litex/gen/fhdl/module.py", line 12, in <module>
    from litex.soc.integration.doc import AutoDoc
  File "/home/pef/DEMO_BAOCHIP/baochip-1x/deps/litex/litex/soc/integration/doc.py", line 10, in <module>
    from litex.soc.interconnect.csr_eventmanager import EventManager
ImportError: cannot import name 'EventManager' from partially initialized module 'litex.soc.interconnect.csr_eventmanager' (most likely due to a circular import) (/home/pef/DEMO_BAOCHIP/baochip-1x/deps/litex/litex/soc/interconnect/csr_eventmanager.py)

Could you help me ?

I've tried also to build the core for an Arty-A7 100T without success:

❯ python3 arty_bio.py
Traceback (most recent call last):
  File "/home/pef/DEMO_BAOCHIP/baochip-1x/arty/arty_bio.py", line 24, in <module>
    from litex.soc.integration.soc import SoCRegion
  File "/home/pef/DEMO_BAOCHIP/baochip-1x/deps/litex/litex/soc/integration/soc.py", line 2158, in <module>
    from litex.build.parser import LiteXArgumentParser
  File "/home/pef/DEMO_BAOCHIP/baochip-1x/deps/litex/litex/build/parser.py", line 13, in <module>
    from litex.soc.cores import cpu
  File "/home/pef/DEMO_BAOCHIP/baochip-1x/deps/litex/litex/soc/cores/cpu/__init__.py", line 122, in <module>
    CPUS = collect_cpus()
  File "/home/pef/DEMO_BAOCHIP/baochip-1x/deps/litex/litex/soc/cores/cpu/__init__.py", line 115, in collect_cpus
    for cpu_name, cpu_cls in inspect.getmembers(importlib.import_module(cpu), inspect.isclass):
                                                ~~~~~~~~~~~~~~~~~~~~~~~^^^^^
  File "/usr/lib/python3.13/importlib/__init__.py", line 88, in import_module
    return _bootstrap._gcd_import(name[level:], package, level)
           ~~~~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/home/pef/DEMO_BAOCHIP/baochip-1x/deps/litex/litex/soc/cores/cpu/vexiiriscv_cramsoc/__init__.py", line 1, in <module>
    from litex.soc.cores.cpu.vexiiriscv_cramsoc.core import VexiiRiscvCramsoc
  File "/home/pef/DEMO_BAOCHIP/baochip-1x/deps/litex/litex/soc/cores/cpu/vexiiriscv_cramsoc/__init__.py", line 1, in <module>
    from litex.soc.cores.cpu.vexiiriscv_cramsoc.core import VexiiRiscvCramsoc
  File "/home/pef/DEMO_BAOCHIP/baochip-1x/deps/litex/litex/soc/cores/cpu/vexiiriscv_cramsoc/core.py", line 19, in <module>
    from soc_oss.axi_axil_adapter import AXI2AXILiteAdapter
ModuleNotFoundError: No module named 'soc_oss'

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